positive and negative edge detection circuits

In many real-life design situations, we often need to use edge detection circuits. One needs to know when a particular signal transitions from low to high or vice versa.

To generate this circuit, we need to have a delayed version of the same signal.

Here is the code snippet for the same in SystemVerilog:

logic  clk;
logic  rst_n;
logic  signal;
logic  signal_d1;

always_ff @(posedge clk or negedge rst_n)
   if (!rst_n)   signal_d <= 1'b0;
  else            signal_d <= signal;

 // Posedge signal detection
 if ( signal && ~signal_d)
   //...

// Negedge signal detection

 if ( ~signal && signal_d)

   //...

// Pulse generation at the posedge signal

assign pulse = signal && ~signla_d;